Apple and NVIDIA to Rival Over Tsmc’s Advanced Packaging
Apple and NVIDIA, two giants in the semiconductor industry, are poised to enter direct competition for TSMC’s advanced 3D packaging resources as Apple prepares to launch its M5 Ultra or M6 Ultra chips. Previously, the two companies operated in largely separate domains within TSMC’s fabrication facilities, with Apple relying on the fab’s cutting-edge InFO (Integrated Fan-Out) packaging for its A-series and M-series processors, while NVIDIA utilised older generation processes and CoWoS (Chip-on-Wafer-on-Substrate) packaging technology for its GPUs. However, this clear division is now blurring as both companies adopt more aggressive chip designs that demand similar advanced packaging technologies.
Details on Apple’s Packaging Innovations
Apple has traditionally used InFO-PoP packaging, where DRAM is stacked directly on top of the system-on-chip (SoC). This approach has been effective for Apple’s A-series and M-series chips, but the company is shifting gears with its upcoming A20 chips by adopting WMCM (Wafer Multi-Chip Module) packaging. This technology enables the integration of multiple individual dies—such as the CPU, GPU, and Neural Engine—into a single package, offering unprecedented flexibility in chip configurations.
Moreover, Apple is expected to employ TSMC’s SoIC-MH (System on Integrated Chips – Multi-Hybrid) packaging for the forthcoming M5 Pro and M5 Max chips. SoIC is a 3D packaging solution that allows both horizontal and vertical stacking of multiple chips into a single SoC-like package, enhancing performance and efficiency. Alongside this, Apple plans to use a new Liquid Moulding Compound (LMC) supplied exclusively by Taiwan’s Eternal Materials. This LMC is specifically engineered to meet the stringent requirements of TSMC’s CoWoS packaging, hinting at Apple’s eventual move towards CoWoS for its M-series processors.
Competition for TSMC’s Packaging Capacity
Industry analysis from Semianalysis highlights that Apple currently dominates TSMC’s AP3 (InFO) packaging segment, while NVIDIA leads in AP5 and AP6, which use CoWoS technology. However, as Apple transitions to the M5 and M6 Ultra chips utilising SoIC and WMCM packaging, both Apple and NVIDIA will begin contending for the same advanced 3D packaging resources in TSMC’s AP6 and AP7 nodes. This convergence raises concerns about capacity allocation and potential bottlenecks within TSMC’s advanced packaging division.
TSMC has recently started outsourcing some of its advanced packaging orders to third-party companies like Taiwan’s ASE and the US’s Amkor, reflecting the growing demand and capacity constraints. This move is a response to the explosion in AI chip orders and the increasing complexity of packaging technologies.
Implications and Future Outlook
Given the intense competition for TSMC’s advanced packaging capabilities, Apple may face challenges securing sufficient capacity for its high-end M-series chips. Analysts suggest this could prompt Apple to diversify its chip production by partnering more closely with other foundries such as Intel and Samsung. In fact, Apple is already evaluating Intel’s 18A-P process for its entry-level M-series chips expected to launch in 2027. SemiAnalysis estimates that if Apple shifts around 20 percent of its base M-series wafer production to Intel, it could generate approximately $630 million in foundry revenue for Intel.
This evolving landscape underscores the strategic importance of advanced packaging technologies in the semiconductor industry and the potential shifts in supplier relationships as demand for sophisticated chips continues to grow.
As Apple and NVIDIA gear up for this packaging showdown, it will be interesting to see how TSMC manages capacity and whether Apple’s diversification strategy will reshape the chip manufacturing ecosystem in the coming years.
Overall, the competition for TSMC’s 3D packaging resources marks a significant development in the semiconductor sector, signalling tighter resource allocation and possibly new partnerships on the horizon.